Japanese patent application no. 11-371190, filed Dec. 27, 1999, is hereby incorporated by reference in its entirety. Japanese patent application no. 2000-374379, filed Dec. 8, 2000, is hereby incorporated by reference in its entirety.
Embodiments of the present invention relates to monolithic integrated circuits, including semiconductor devices having transistors with low breakdown voltage and transistors with high breakdown voltage that form a very miniaturized integrated circuit.
LSI chips are diversified, and higher device integration, further size reduction and lower power consumption are required for the diversified LSI chips. One type of integrated circuit mix-mounts a logic section that is composed of transistors with low breakdown voltage and an input/output circuit that is composed of transistors with high breakdown voltage.
In a region where transistors with high breakdown voltage are disposed (hereafter referred to as xe2x80x9chigh breakdown voltage transistor regionxe2x80x9d), an element isolation dielectric region generally needs to have a film thickness greater than a film thickness of an element isolation dielectric region in a region where transistors with low breakdown voltage are disposed (hereafter referred to as xe2x80x9clow breakdown voltage transistor regionxe2x80x9d) in order to attain a higher breakdown voltage. For example, when a power supply voltage is 20 V, an element isolation dielectric region in a high breakdown voltage transistor region needs to have a film thickness of about 900 nm. When a power supply voltage is 40 V, an element isolation dielectric region in a high breakdown voltage transistor region needs to have a film thickness of about 1400 nm.
When an element isolation dielectric region in a high voltage breakdown or high dielectric strength transistor region does not have a sufficient film thickness, an impurity concentration of an inversion prevention layer (i.e., a channel stopper layer) that prevents an operation of a parasitic MOS transistor may be made higher. Such a measure may deal with the insufficiency in the film thickness. However, the impurity concentration of such an inversion prevention layer is restricted to a specified range, and therefore the range of potentials that can be dealt with by the adjustment of impurity concentration is limited.
In a low breakdown voltage transistor region, where transistors with low breakdown voltage are manufactured under a 0.8 xcexcm rule or lower, the thickness of an element isolation dielectric film by LOCOS (Local Oxidation of Silicon) is restricted to a specified range (for example, about 600 nm). Such a film thickness is required because of the miniaturized transistor elements. More specifically, as the transistor elements are miniaturized, an interlayer dielectric film is also made thinner in areas over a semiconductor substrate where transistors with low breakdown voltage and transistors with high breakdown voltage are formed. To reduce a step difference in the interlayer dielectric film at an element isolation dielectric region, the thickness of the element isolation dielectric region needs to be relatively small.
It is difficult to incorporate transistors with high breakdown voltage in a semiconductor device that is designed under a miniaturized design rule. In other words, when a thick element isolation dielectric film is formed to secure sufficient dielectric strength for transistors with high breakdown voltage, a step difference becomes substantially large at edge sections of the transistors. This makes it difficult to form transistors with low breakdown voltage and circuit wirings for the transistors in some areas over the substrate.
One embodiment relates to a semiconductor device comprising a substrate including a first breakdown voltage transistor area having at least one transistor with a first breakdown voltage and a second breakdown voltage transistor area having at least one transistor with a second breakdown voltage, wherein the first breakdown voltage is greater than the second breakdown voltage. The device also includes an interlayer dielectric film provided over the substrate and a wiring layer provided over the interlayer dielectric film above the transistor with the first breakdown voltage. The device also includes an element isolation dielectric region on the substrate, and at least one fixed potential wiring region in the first breakdown voltage transistor area between the element isolation dielectric region and the wiring layer.
Another embodiment relates to a semiconductor device comprising a substrate including a first breakdown voltage transistor region including a first transistor and a second breakdown voltage transistor region including a second transistor having a breakdown voltage less than that that of the first transistor, wherein the first and second transistors operate at different voltages. The device includes an element isolation dielectric region formed on the substrate to electrically isolate the first transistor from the second transistor, and a guardring region comprising an impurity diffusion region disposed in the semiconductor substrate in the first breakdown voltage transistor region. The device also includes a first interlayer dielectric film disposed over the substrate, and a second interlayer dielectric film disposed over the first interlayer dielectric film. The device also includes a wiring layer including a first wiring portion that is connected to the first transistor and a second wiring portion that is connected to the second transistor. The device also includes a fixed potential wiring region disposed in the first breakdown voltage transistor region between the element isolation dielectric film and the first wiring portion, wherein one of the wiring layer and the fixed potential wiring region is formed on the first interlayer dielectric film and the other of the wiring layer and the fixed potential wiring region is formed on the second interlayer dielectric film.